In recent years, especially in the area of avionics, multiple dissimilar general purpose microprocessor architectures have been used to attain a high level of assurance of integrity of general purpose microprocessor performance. These multiple processors are used in parallel, and their outputs are compared to reduce the likelihood of an undetected processor failure.
While these multiple dissimilar microprocessor architectures have been used extensively in the past, they do have some drawbacks. First of all, these architectures often use commercially available general purpose processors because of their relatively high performance and low cost. However, these processors, with their ever-increasing size, have increased capacity for bugs or defects. Therefore, with each increase in microprocessor size, which is heralded by the PC community, there is an actual reduction in assurance level. Additionally, when attempting to run the same program on dissimilar processors for avionics equipment, it is necessary to compile and maintain, over the service life of the product (which can often be in excess of thirty years), distinct versions for each of the dissimilar processors. This can be expensive.
Yet another drawback of dissimilar processors is the level of complexity typically involved in achieving communication between the dissimilar processors.
Consequently, there exists a need for economically efficient improved methods and systems for providing enhanced microprocessor integrity without the need for maintaining multiple versions of each of the various applications which run on the multiple processor system.